Synopsys has announced the commercial availability of the first set of its Multiphysics Fusion solutions, introducing an integrated design platform that combines electronic design automation (EDA) technologies with advanced multiphysics analysis. The new portfolio is designed to help semiconductor companies overcome the growing design challenges associated with artificial intelligence (AI), high-performance computing (HPC), advanced process nodes and multi-die architectures.
As semiconductor devices become increasingly complex, engineers must simultaneously address issues such as signal integrity, power delivery, thermal management, electromagnetic interference and packaging constraints. Traditional design approaches often require multiple independent verification cycles, extending development timelines and increasing engineering costs. Synopsys’ new Multiphysics Fusion platform aims to streamline this process by bringing these disciplines together within a unified workflow.
The solution integrates Synopsys’ AI-enabled EDA technologies with Ansys’ signoff analysis capabilities, enabling designers to account for physical effects throughout the chip development process rather than addressing them during final verification. The result is faster design convergence, improved predictability and better silicon performance.
According to Synopsys, the initial release focuses on digital and analog design workflows, including timing signoff, design closure and multi-die development. The company said the integrated environment enables engineering teams to identify potential performance issues earlier, reducing the number of design iterations required before tape-out.
One of the key offerings in the portfolio is Multiphysics Fusion for Timing Signoff. The solution combines Synopsys PrimeTime, StarRC, RedHawk-SC and RedHawk-SC Electrothermal technologies with HFSS-IC electromagnetic analysis to provide highly accurate timing verification while incorporating the effects of voltage drop, temperature variations and mechanical stress. GPU acceleration powered by NVIDIA CUDA-X libraries significantly reduces analysis time, delivering runtime improvements of up to three times compared with conventional methods.
The platform has already been evaluated by leading semiconductor companies. Cisco’s Silicon One engineering team is using the technology to incorporate power integrity analysis directly into the design closure process. By combining timing-aware IR-drop correction with signoff-level accuracy, engineers can identify potential reliability issues much earlier, improving power, performance and area (PPA) while reducing overall design cycles.
Synopsys said the new solutions reflect the industry’s shift toward system-aware chip development, where multiple engineering disciplines must work together to meet the demands of next-generation AI infrastructure and advanced computing systems. As semiconductor designs continue to scale in complexity, integrated multiphysics analysis is expected to become an essential part of future chip development, helping manufacturers deliver higher-performance products with greater efficiency and reduced development risk.
